Verilog:

module vl_2-bit_greater-than(a1, a0, b1, b0, gt);
input a1, a0, b1, b0;
output gt;
wire e0, e1, e2, e3, e4, e5, e6;
nor u0(e0, b1, b0);
not u1(a1, e1);
not u2(b0, e2);
nor u3(e3, a1, e0);
nor u4(e4, b1, e1);
and u5(e5, a0, e2);
nor u6(e6, e4, e5);
nor u7(gt, e3, e6);
endmodule


VHDL:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- ===========================================

ENTITY 2-bit_greater-than IS
  PORT (
    a1 : IN BIT;
    a0 : IN BIT;
    b1 : IN BIT;
    b0 : IN BIT;
    gt : OUT BIT
  );
END 2-bit_greater-than;
-- ===========================================

ARCHITECTURE gate_level OF 2-bit_greater-than IS

COMPONENT not1 PORT (a1: IN BIT; z: OUT BIT); END COMPONENT;

-- Intermediate nets
  SIGNAL e0, e1, e2, e3, e4, e5, e6 : BIT;

BEGIN
  U0 : nor2 PORT MAP (b1, b0, e0);
  U1 : not1 PORT MAP (a1, e1);
  U2 : not1 PORT MAP (b0, e2);
  U3 : nor2 PORT MAP (a1, e0, e3);
  U4 : nor2 PORT MAP (b1, e1, e4);
  U5 : and2 PORT MAP (a0, e2, e5);
  U6 : nor2 PORT MAP (e4, e5, e6);
  U7 : nor2 PORT MAP (e3, e6, gt);

END gate_level;